// Showcase
Safety-related control needs a processor that can demonstrate it is working – integrated diagnostics, error correction on every memory, and a development flow certified against IEC 61508 and ISO 26262.
Safety-related control needs a processor that can demonstrate it is working – integrated diagnostics, error correction on every memory, and a development flow certified against IEC 61508 and ISO 26262. What such a chip does not come with is an assembly. Between a certified microcontroller and a finished product sit memory, power supply, watchdog, Ethernet connection – and a software stack that almost everybody underestimates.
By building that intermediate layer once as a product of its own instead of rebuilding it in every customer project. The result is a module of 35 × 38 × 10 mm with a 32-bit RISC core, 3 MB of program flash and 256 KB of RAM – both with error correction – 16 MB SDRAM, 256 KB of ferroelectric memory, an external watchdog and a single 5 V supply. Plus three CAN channels, LIN, up to five SPI, I²C, PWM, USB and 10/100 Mbps Ethernet with IEEE 1588 time synchronisation. And a software package that ships with it: real-time operating system, TFTP bootloader, command line over UDP, TCP/UDP, network time protocol, FAT file system, HTTP server, WebSocket, FTP.
A start on day one instead of in week three. The debug board carries the USB-JTAG emulator on board, supports the trace buffer, runs on 500 mA from the USB port and already has the network connector fitted – no separate emulator, no power supply, no adapter cable to hunt for. The evaluation board is deliberately over-equipped: power over Ethernet at 24 W, 21 analogue inputs, 8 analogue outputs, three CAN interfaces, microSD, temperature sensor, potentiometers, LEDs and switches. Nobody needs all of it – but the answer to "can it also do X?" is then always yes, and on the same afternoon.
A product family out of a single development: module, debug board, evaluation board – plus a debug probe that appears only in the costing sheet. The effort behind it: 0.8 man-years, roughly 70 % of it on the module and 30 % on the debug board. The ferroelectric memory, which permanently occupies one of the five SPI channels, is incidentally exactly where a safety device puts what it must not lose when the power fails.
The most instructive document in the folder is the costing sheet. The plan is 5 modules in the first year, 20 in the second and 50 in the third – 75 in total. Spread over that quantity, amortising the development accounts for around 83 % of the price, while components, board and roughly 0.85 hours of assembly per unit together make up about one sixth. That is the entire economics of a small-series platform in one line – and at the same time the argument for building the intermediate layer once rather than paying for it in every project.
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